Interconnect structure of semiconductor device and method for manufacturing same

ABSTRACT

An interconnect structure of a semiconductor device includes: a bottom interconnect layer formed in a dielectric layer overlying a silicon substrate; a top interconnect layer having aluminum as a main component and connected with the bottom interconnect layer by way of a via plug formed in the dielectric layer; and a first barrier metal layer having higher &lt;111&gt; orientation. The higher &lt;111&gt; orientation degree of the first barrier metal layer aluminum suppresses occurrence and growth of electro-migration provide a reliable interconnect structure.

BACKGROUND OF THE INVENTION

[0001] (a) Field of the Invention

[0002] The present invention relates to an interconnect structure of asemiconductor device and a method for manufacturing the same, more indetail, to the multiple-layered interconnect structure having aluminumas a main component which can suppress occurrence and growth ofelectro-migration (EM) the method of manufacturing the same.

[0003] (b) Description of the Related Art

[0004] With the advance of high integration of semiconductor devices,the multi-layered interconnect structure in which a plurality ofinterconnect layers are connected to one another is more and morecomplicated.

[0005] An example of a method for manufacturing a conventionalmulti-layered interconnect structure will be described referring toFIGS. 1A to 1F.

[0006] A bottom interconnect layer 14 is deposited on an undercoatdielectric film 12 overlying a silicon substrate (not shown), and aninterlayer dielectric film 16 made of a plasma oxide is formed andflattened on the bottom interconnect layer 14 as shown in FIG. 1A.

[0007] The bottom interconnect layer 14 includes, for example, an Al—Cualloy film 14 a constituting a main interconnect body, a Ti layer 14 bformed thereon and having a thickness of 25 nm, and a first TiN layer 14c having a thickness of 50 nm formed as a reflection preventing film ina photolithographic process. The Ti layer is formed for preventingformation of AlN during deposition of a first TiN layer As shown in FIG.1B, a through-hole 18 is formed in the interlayer dielectric film 16 toreach to the bottom interconnect layer 14 by a lithographic and etchingprocess.

[0008] Then, as shown in FIG. 1C, a second TiN layer 20 is formed as abarrier metal layer on the entire surface of the wafer including thewalls of the connection aperture 18 followed by formation of a tungsten(W) layer 22 on the second TiN layer 20.

[0009] Then, as shown in FIG. 1D, the tungsten layer 22 is etched-backby employing a plasma etching method until the second TiN layer 20 isexposed, thereby forming a plug 24 of tungsten.

[0010] Then, as shown in FIG. 1E, a third TiN layer 26 having athickness of 40 nm is deposited as a barrier metal layer on the secondTiN layer 20, followed by deposition of an Al—Cu alloy layer 28 on thethird TiN layer 26 by sputtering at a temperature of 340° C. After theAl—Cu alloy layer 28 is cooled for 50 seconds, a Ti layer 30 having athickness of 25 nm and a TiN layer 32 having a thickness of 50 nm aresequentially deposited on the Al—Cu alloy layer 28 by sputtering to forma top interconnect layer 34.

[0011] The TiN layer 26 prevents excessive increase of a contactresistance between the Al—Cu alloy layer 28 and the tungsten layer 22even if a void is formed in the Al—Cu alloy layer 28 on the plug 24 dueto the EM.

[0012] Patterning of the TiN layer 32, the Ti Layer 30, the Al—Cu alloylayer 28, the third TiN layer 26 and the second TiN layer 20 by alithographic and dry-etching treatment provides top interconnects 34having a desired interconnect pattern.

[0013] In the above conventional interconnect structure, with theminiaturization thereof, the lifetime of the interconnect isconsiderably reduced due to the EM of the Al—Cu alloy layer to increasethe interconnect resistance during the operation, and finally aninterconnect deficiency such as a break down may be generated.

[0014] Since current is likely to be concentrated to the interconnectright above the plug, migration of the aluminum due to the EM may easilyoccur to make a void.

SUMMARY OF THE INVENTION

[0015] In view of the foregoing, an object of the present invention isto provide an interconnect structure which can suppress occurrence andgrowth of the EM of the aluminum and a method for manufacturing thesame.

[0016] The present invention provides, in a first aspect thereof, aninterconnect structure of a semiconductor device including: a siliconsubstrate; a bottom interconnect layer formed in a dielectric layeroverlying the silicon substrate; a top interconnect layer havingaluminum as a main component and connected with the bottom interconnectlayer by way of a via plug formed in the dielectric layer; and a <111>oriented first barrier metal layer disposed between the via plug and thetop interconnect layer.

[0017] The present invention provides, in a second aspect thereof, amethod for manufacturing an interconnect structure of a semiconductordevice, including the steps of: forming a bottom interconnect layerunderlying a dielectric layer and overlying a silicon substrate; forminga through-hole in the dielectric layer to expose the bottom interconnectlayer; depositing a first barrier metal layer overlying the dielectriclayer and on an inner wall of the through-hole; depositing a metal layeron the first barrier metal layer for filling the through-hole; etchingthe metal layer and the first barrier metal layer until the dielectricfilm is exposed to thereby form a via plug of the metal layer and thebarrier metal layer; depositing a second barrier metal layer on thedielectric film and the via plug; and depositing an interconnect layerof which a main component is aluminum on the second barrier metal layer.

[0018] In accordance with the interconnect structure of the presentinvention and fabrication from the method of the present invention, theincreased <111> orientation of the aluminum of the top interconnectssuppress the occurrence and the growth of the EM of the aluminum.Accordingly, substantially no interconnect deficiencies due to the EMare generated to provide a reliable interconnect structure.

[0019] The above and other objects, features and advantages of thepresent invention will be more apparent from the following description.

BRIEF DESCRIPTION OF DRAWINGS

[0020]FIGS. 1A to 1F are vertical sectional views sequentially showing aseries of steps of manufacturing a conventional semiconductor device.

[0021]FIG. 2 is a graph showing relations between an average troubleoccurring period and <111> orientation of aluminum and between theaverage trouble occurring period and an average particle size ofaluminum particles.

[0022]FIG. 3 shows graphs regarding a relation between a composition ofa barrier metal layer and the <111> orientation of the aluminum.

[0023]FIG. 4 is a vertical sectional view showing a semiconductor devicehaving a stacked structure in accordance with a first embodiment of thepresent invention.

[0024]FIGS. 5A to 5F are vertical sectional views sequentially showing aseries of manufacturing steps in accordance with a second embodiment ofthe present invention.

PREFERRED EMBODIMENTS OF THE INVENTION

[0025] As a result of investigating reasons of the growth of the EM ofaluminum in a conventional interconnect structure, the present inventorhas found that the EM grows because <111> orientation of the aluminum inan Al—Cu alloy layer with respect to a silicon substrate having theinterconnect structure is extremely low.

[0026] A mean time to failure (MTTF) is closely related with the <111>orientation of the aluminum as shown in a line (L1) in a graph of FIG. 2in which the MTTF is plotted on ordinate and a function of the <111>orientation of the aluminum {(S/σ) log[Al(111)/Al(200)]} on abscissa. Asshown therein, the MTTF increases with the increase of <111> orientationof the aluminum. The relation of the above graph was obtained byemploying an alloy interconnect of Al-0.5% Cu at a temperature of 80° C.and a current density of 1×10⁵ A/cm².

[0027] The trouble of the multi-layered interconnect structure havingthe Al—Cu alloy is mainly caused by the growth of the EM of the aluminumwhich is delayed with the increase of the particle size of the aluminumcrystal. Thus, it is estimated that the growth of the EM the aluminumcan be effectively suppressed with the increase of the <111> orientationof the aluminum which increases a particle size of the aluminum crystal.

[0028] As shown by a line (L2) in the graph of FIG. 2, the MTTFincreases with the increase of the particle lo size of the aluminumcrystal.

[0029] The present inventor has further found that a relation such asshown in graphs of FIGS. 3A and 3B holds between the composition of thebarrier metal layer positioned between the Al—Cu interconnect and thevia plug and the <111> orientation of the aluminum in the Al—Cuinterconnect. In the graphs, FIG. 3A and 3B show XRD analysis resultswhich are obtained by plotting 2θ on abscissa and diffraction strengthof X-rays on ordinate. A certain plane direction of a certain materialcan be determined from the value of 2θ at which the diffraction strengthof X-rays has a peak, and a degree of the orientation of the planedirection can be determined from the peak value of the diffractionstrength of X-rays.

[0030] It can be seen from FIGS. 3A and 3B that when the barrier metallayer includes only the TiN layer, the <111> orientation of the TiNlayer and the aluminum is low and that when the barrier metal layerincludes the Ti layer and the TiN layer, the <111> orientation of theTiN layer and the aluminum is largely elevated.

[0031] In the present invention, the number of the layers of theinterconnect structure is not restricted as far as the top interconnectsare made of a metal or an alloy of which a main component is aluminum.For example, in case of a three-layered interconnect structure, a secondlevel interconnect layer is selected as a bottom interconnect layer anda third level interconnect layer is selected as a top interconnectlayer.

[0032] The first barrier metal layer in the present invention ispreferably a stacked film including a TiN layer and a TiN layer formedthereon. The via plug preferably includes a second barrier metal layerand a tungsten layer. The top interconnect layer is preferably made ofan Al—Cu alloy.

[0033] Thicknesses of the Ti layer and the TiN layer included in thelower portion of the first barrier metal layer are 20 nm or more and 25nm or more, respectively. The thicknesses of the above layers below thespecified values reduce the effect of suppressing the occurrence and thegrowth of the EM of the aluminum.

[0034] The top layers of the dielectric film is preferably made ofplasma oxide which has an excellent CMP-polished ability and an effectof preventing contamination of the substrate with a metal.

[0035] Now, the present invention is more specifically described withreference to accompanying drawings.

[0036] Embodiment with Respect to Interconnect Structure

[0037] An interconnect structure 40 overlying a semiconductor substrate(not shown) of a semiconductor device in accordance with a firstembodiment shown in FIG. 4 includes an undercoat dielectric film 42,bottom interconnects 44 formed thereon, an interlayer dielectric film 46formed around the bottom interconnects 44, a via plug 48 penetrating theinterlayer dielectric film 46 and top interconnects 50 connected to thebottom interconnects 44 by way of the via plug 48.

[0038] The bottom interconnects 44 and the top interconnects 50 arepatterned in accordance with respective specified patterns.

[0039] The bottom interconnects 44 include a first Al—Cu alloy layer 44a constituting an interconnect body, a first Ti layer 44 b having athickness of 25 nm for preventing formation of AlN during deposition ofa first TiN layer, and the first TiN layer 44 c having a thickness of 50nm formed as a reflection preventing film in a photolithographictreatment for patterning an interconnect layer.

[0040] The interlayer dielectric film 46 includes a bottom layer BPSGfilm 46 a and CVD oxide, for example, a SiOF film 46 a formed on theBPSG film 46 a by a plasma CVD method.

[0041] The SiOF film 46 a has an excellent CMP polished ability forforming the via plug 48 and traps, by gettering, a metal, for example,phosphorous (P) in a polishing agent employed in the CMP polishing toeffectively prevent contamination of the substrate with the metal.

[0042] The via plug 48 is formed by filling a connection aperture, witha via plug forming material, partially penetrating the interlayerdielectric film 46 to expose the bottom interconnects 44, and includes asecond TiN layer 48 a formed as a barrier metal layer on the wall of theconnection aperture including the bottom surface, and a tungsten layer48 b formed by filling the connection aperture.

[0043] The top interconnects 50 include a first stacked barrier metallayer 52 having a second Ti layer 52 a of a thickness of 20 nm and athird TiN layer 52 b on the second Ti layer 52 a deposited on the viaplug 48, a second Al—Cu alloy layer (top interconnect layer) 50 aconstituting a main interconnect of the top interconnects 50, a third Tilayer 50 b for preventing formation of AlN during deposition of a fourthTiN layer on the second Al—Cu alloy layer 50 a and the fourth TiN layer50 c formed as a reflection preventing film in a photolithographictreatment for patterning an interconnect layer.

[0044] The second Al—Cu alloy layer 50 a consists of, for example, 0.5%in weight of copper and a balance of aluminum.

[0045] Thicknesses of the second Al—Cu alloy layer 50 a, the third Tilayer 50 b and the fourth TiN layer 50 c are 450 nm, 25 nm and 50 nm,respectively.

[0046] Since the first stacked barrier metal layer 52 of the topinterconnects 50 in the interconnect structure 40 of the firstembodiment includes the second Ti layer 52 a and the third TiN layer 52b having higher <111> orientation, the <111> orientation of the aluminumin the second Al—Cu alloy layer 50 a of the top interconnects 50 isextremely high to noticeably suppress the occurrence and the growth ofthe EM of the aluminum. Substantially no interconnect deficiency due tothe EM provides the interconnect structure having high reliability.

[0047] After an interconnect sample was manufactured having a similarstructure to the interconnect structure 40 of the first embodiment shownin FIG. 4, a life test of the sample was conducted. It was observed thatan average trouble occurring period was prolonged to about 2.5 timescompared with that of the conventional interconnect structure shown inFIGS. 1A to 1F.

[0048] Embodiment with Respect to Manufacture of Interconnect Structure

[0049] An example of manufacturing the interconnect structure of thefirst embodiment shown in FIG. 4 will be described, as a secondembodiment, referring to FIGS. 5A to 5F sequentially showing therespective steps of the manufacture.

[0050] At first, the bottom interconnects 44 are formed on the undercoatdielectric film 42 overlying the silicon substrate (not shown) as shownin FIG. 5A.

[0051] As the bottom interconnects 44, the first Al—Cu alloy layer 44 aconstituting the main interconnect, the first Ti layer 44 b having athickness of 25 nm and the first TiN layer 44 c having a thickness of 50nm are sequentially deposited by sputtering.

[0052] The BPSG film 46 a and the SiOF film 46 b are sequentially formedon the bottom interconnects 44 to provide the interlayer dielectric film46. The SiOF film 46 b is formed by a plasma CVD method and thereafterflattened The SiOF film 46 a has an excellent CMP polished ability forforming the via plug 48 and traps a metal to effectively preventcontamination of the substrate with the metal.

[0053] As shown in FIG. 5B, the connection aperture 47 is formedpartially penetrating the interlayer dielectric film 46 including theSiOF film 46 b and the BPSG film 46 a to reach to the bottominterconnects 44 by means of a lithographic etching treatment.

[0054] Then, as shown in FIG. 5C, the second TiN layer 48 a as a secondbarrier metal layer is formed on the entire surface of the substrateincluding the wall of the connection aperture 47, and the tungsten layer48 b is formed on the second TiN layer 48 a.

[0055] Thereafter, the tungsten layer 48 b and the second TiN layer 48 aare removed by CMP polishing until the SiOF film 46 b is exposed forforming the via plug 48 as shown in FIG. 5D.

[0056] The barrier metal layer, when formed on the SiOF film 46 bflattened by the CMP polishing having a high degree of flatness, hashigher <111> orientation.

[0057] Then, as shown in FIG. 5E, the stacked barrier metal layer 52including the second Ti layer 52 a having a thickness of 20 nm and thethird TiN layer 52 b having a thickness of 40 nm is deposited, as thebarrier metal layer, on the via plug 48 and the SiOF film 46 b bysputtering.

[0058] The second Ti layer 52 a is deposited by sputtering withoutback-heating while an argon gas is flown at 35 sccm, and after theformation of the second Ti layer 52 a, the third TiN layer 52 b iscontinuously deposited by sputtering without back-heating while an argongas and a nitrogen gas are flown at 57 sccm and 85 sccm, respectively.The “continuos deposition” in the present invention means that thelatter deposition is conducted in the same sputtering apparatus as thatemployed in the former deposition or the latter deposition is conductedwithout any other treatment after the wafer is conveyed from thesputtering apparatus to another in a non-oxidative ambient.

[0059] After the formation of the third TiN layer 52 b, the second Al—Cualloy layer 50 a having a thickness of 450 nm constituting the maininterconnect of the top interconnects 50 is continuously deposited onthe third TiN layer 52 b while an argon gas is flown at 35 sccm bysputtering at a temperature of 340° C. The second Al—Cu alloy layer 50 aconsists of, for example, 0.5% in weight of copper and a balance ofaluminum.

[0060] After the deposition of the second Al—Cu alloy layer 50 a,cooling is conducted by leaving the wafer in a cooling chamber for about60 seconds until the temperature in the chamber is lowered to 200° C.

[0061] On the second Al—Cu alloy layer 50 a, another stacked barriermetal layer including the third Ti layer 50 b having a thickness of 25nm for preventing formation of AlN during the deposition of the fourthTiN layer 50 c and the fourth TiN layer 50 c having a thickness of 50 nmformed as a reflection preventing film in a photolithographic treatmentfor patterning an interconnect layer is deposited by sputtering.

[0062] The third Ti layer 50 b can be formed without back-heating whilean argon gas is flown at 35 sccm, and the fourth TiN layer 50 c can bedeposited by sputtering without back-heating while an argon gas and anitrogen gas are flown at 57 sccm and 85 sccm, respectively.

[0063] Then, the fourth TiN layer 50 c, the third Ti layer 50 b, thesecond Al—Cu alloy layer 50 a, the third TiN layer 52 b and the secondTi layer 52 a are patterned by a lithographic dry etching treatment toform the top interconnects 50 having a desired interconnect pattern asshown in FIG. 5F.

[0064] Since the above embodiments are described only for examples, thepresent invention is not limited to the above embodiments and variousmodifications or alternations can be easily made therefrom by thoseskilled in the art without departing from the scope of the presentinvention.

What is claimed is:
 1. An interconnect structure of a semiconductordevice comprising: a silicon substrate; a bottom interconnect layerformed in a dielectric layer overlying the silicon substrate; a topinterconnect layer having aluminum as a main component and connectedwith the bottom interconnect layer by way of a via plug formed in thedielectric layer; and a <111> oriented first barrier metal layerdisposed between the via plug and the top interconnect layer.
 2. Theinterconnect structure as defined in claim 1 , wherein the first barriermetal layer is a stacked film including a Ti layer and a TiN layerdisposed thereon.
 3. The interconnect structure as defined in claim 1 ,wherein the via plug includes a second barrier metal layer and atungsten layer, and the top interconnect layer is made of an Al—Cualloy.
 4. The interconnect structure as defined in claim 2 , whereinthicknesses of the Ti layer and the TiN layer of the first barrier metallayer are not less than 20 nm and not less than 25 nm, respectively. 5.The interconnect structure as defined in claim 1 , wherein a top layerof the dielectric layer is made of plasma oxide.
 6. A method formanufacturing an interconnect structure of a semiconductor device,comprising the steps of: forming a bottom interconnect layer underlyinga dielectric layer and overlying a silicon substrate; forming athrough-hole in the dielectric layer to expose the bottom interconnectlayer; depositing a first barrier metal layer overlying the dielectriclayer and on an inner wall of the through-hole; depositing a metal layeron the first barrier metal layer for filling the through-hole; etchingthe metal layer and the first barrier metal layer until the dielectricfilm is exposed to thereby form a via plug of the metal layer and thebarrier metal layer; depositing a second barrier metal layer on thedielectric film and the via plug; and depositing an interconnect layerof which a main component is aluminum on the second barrier metal layer.7. The method as defined in claim 6 , wherein the second barrier metallayer is formed by sequentially depositing a Ti layer and a TiN layer bysputtering.
 8. The method as defined in claim 6 , wherein CMP polishingis employed for removing the metal layer and the first barrier metallayer in the via plug forming step.
 9. The method as defined in claim 7, wherein the TiN layer is continuously deposited by sputtering afterthe deposition of the Ti layer.
 10. The method as defined in claim 7 ,wherein the interconnect layer is continuously deposited by sputteringafter the deposition of the TiN layer.
 11. The method as defined inclaim 7 further comprising a Ti layer and a TiN layer on theinterconnect layer which are deposited after the interconnect layer iscooled for a specified period of time upon the completion of theinterconnect layer depositing step.
 12. The method as defined in claim 6, wherein the interconnect layer is made of an Al—Cu alloy.
 13. Themethod as defined in claim 6 , wherein the interconnect layer is <111>oriented.